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| 2.1 On Resistance, 15 V/+12 V/5 V iCMOS SPDT Switch ADG1419 FEATURES 2.1 on resistance 0.5 maximum on resistance flatness at 25C Up to 390 mA continuous current Fully specified at +12 V, 15 V, 5 V No VL supply required 3 V logic-compatible inputs Rail-to-rail operation 8-lead MSOP and 8-lead 3 mm x 2 mm LFCSP packages FUNCTIONAL BLOCK DIAGRAM ADG1419 LFCSP SA D SB DECODER EN IN SWITCHES SHOWN FOR A LOGIC 0 INPUT. Figure 1. 8-Lead LFCSP Functional Block Diagram APPLICATIONS Automatic test equipment Data acquisition systems Battery-powered systems Relay replacements Sample-and-hold systems Audio signal routing Video signal routing Communication systems ADG1419 MSOP SA D SB IN SWITCHES SHOWN FOR A LOGIC 0 INPUT. Figure 2. 8-Lead MSOP Functional Block Diagram GENERAL DESCRIPTION The ADG1419 is a monolithic iCMOS(R) device containing a single-pole/double-throw (SPDT) switch. An EN input on the LFCSP package is used to enable or disable the device. When disabled, all channels are switched off. The iCMOS (industrial CMOS) modular manufacturing process combines high voltage, complementary metal-oxide semiconductor (CMOS) and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no other generation of high voltage parts has achieved. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. The on resistance profile is very flat over the full analog input range ensuring excellent linearity and low distortion when switching audio signals. The iCMOS construction ensures ultralow power dissipation, making the part ideally suited for portable and battery-powered instruments. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. The ADG1419 exhibits break-before-make switching action for use in multiplexer applications. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. 2.4 maximum on resistance at 25C. Minimum distortion. 3 V logic-compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V. No VL logic power supply required. 8-lead MSOP and 8-lead, 3 mm x 2 mm LFCSP packages. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved. 08485-002 08485-001 ADG1419 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 15 V Dual Supply ....................................................................... 3 +12 V Single Supply ..................................................................... 4 5 V Dual Supply ......................................................................... 5 Continuous Current Per Channel, S or D ................................. 6 Absolute Maximum Ratings ............................................................7 Thermal Resistance .......................................................................7 ESD Caution...................................................................................7 Pin Configuration and Function Descriptions..............................8 Typical Performance Characteristics ..............................................9 Test Circuits ..................................................................................... 12 Terminology .................................................................................... 14 Outline Dimensions ....................................................................... 15 Ordering Guide .......................................................................... 15 REVISION HISTORY 10/09--Revision 0: Initial Version Rev. 0 | Page 2 of 16 ADG1419 SPECIFICATIONS 15 V DUAL SUPPLY VDD = +15 V 10%, VSS = -15 V 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On Resistance Match Between Channels, RON On Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise -3 dB Bandwidth Insertion Loss CS (Off ) CD (Off ) CD, CS (On) 25C -40C to +85C -40C to +125C VDD to VSS 2.1 2.4 0.05 0.2 0.4 0.5 0.1 0.5 0.2 0.6 0.2 1 2.8 0.25 0.6 3.2 0.3 0.65 Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ MHz typ dB typ pF typ pF typ pF typ Test Conditions/Comments VS = 10 V, IS = -10 mA; see Figure 22 VDD = +13.5 V, VSS = -13.5 V VS = 10 V, IS = -10 mA VS = 10 V, IS = -10 mA VDD = +16.5 V, VSS = -16.5 V VS = 10 V, VS = 10 V; see Figure 23 VS = 10 V, VS = 10 V; see Figure 23 VS = VD = 10 V; see Figure 24 2 3 3 75 100 100 2.0 0.8 0.005 0.1 4 130 155 85 110 115 140 15 -16 -64 -64 0.016 135 0.16 19 44 114 VIN = VGND or VDD 190 125 160 220 140 180 8 RL = 300 , CL = 35 pF VS = +10 V; see Figure 25 RL = 300 , CL = 35 pF VS = 10 V; see Figure 27 RL = 300 , CL = 35 pF VS = 10 V; see Figure 27 RL = 300 , CL = 35 pF VS1 = VS2 = 10 V; see Figure 26 VS = 0 V, RS = 0 , CL = 1 nF; see Figure 28 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 29 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 30 RL = 10 k, 5 V rms, f = 20 Hz to 20 kHz; see Figure 32 RL = 50 , CL = 5 pF; see Figure 31 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 31 f = 1 MHz; VS = 0 V f = 1 MHz; VS = 0 V f = 1 MHz; VS = 0 V Rev. 0 | Page 3 of 16 ADG1419 Parameter POWER REQUIREMENTS IDD IDD, 8-Lead MSOP IDD, 8-Lead LFCSP ISS VDD/VSS 1 25C 0.002 -40C to +85C -40C to +125C Unit A typ A max A typ A max A typ A max A typ A max V min/max Test Conditions/Comments VDD = +16.5 V, VSS = -16.5 V Digital inputs = 0 V or VDD Digital inputs = 5 V Digital inputs = 5 V Digital inputs = 0 V, 5 V or VDD Ground = 0 V 1.0 58 95 120 190 0.002 1.0 4.5/16.5 Guaranteed by design, not subject to production test. +12 V SINGLE SUPPLY VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On Resistance Match Between Channels, RON On Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD Charge Injection Off Isolation 25C -40C to +85C -40C to +125C 0 V to VDD 4 4.6 0.08 0.25 1.2 1.5 0.1 0.5 0.2 0.6 0.2 1 5.5 0.3 1.75 6.2 0.35 1.9 Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ Test Conditions/Comments VS = 0 V to 10 V, IS = -10 mA; see Figure 22 VDD = +10.8 V, VSS = 0 V VS = 0 V to 10 V, IS = -10 mA VS = 0 V to 10 V, IS = -10 mA VDD = +13.2 V, VSS = 0 V VS = 1 V/10 V, VD = 10 V/1 V; see Figure 23 VS = 1 V/10 V, VD = 10 V/1 V; see Figure 23 VS = VD = 1 V or 10 V; see Figure 24 2 3 3 75 100 100 2.0 0.8 0.005 0.1 4 200 255 145 190 130 170 55 13 -60 VIN = VGND or VDD 265 220 205 370 245 220 33 RL = 300 , CL = 35 pF VS = 8 V; see Figure 25 RL = 300 , CL = 35 pF VS = 8 V; see Figure 27 RL = 300 , CL = 35 pF VS = 8 V; see Figure 27 RL = 300 , CL = 35 pF VS1 = VS2 = 8 V; see Figure 26 VS = 6 V, RS = 0 , CL = 1 nF; see Figure 28 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 29 Rev. 0 | Page 4 of 16 ADG1419 Parameter Channel-to-Channel Crosstalk -3 dB Bandwidth Insertion Loss CS (Off ) CD (Off ) CD, CS (On) POWER REQUIREMENTS IDD IDD, 8-Lead MSOP IDD, 8-Lead LFCSP VDD 1 25C -60 95 0.3 32 72 123 0.001 -40C to +85C -40C to +125C Unit dB typ MHz typ dB typ pF typ pF typ pF typ A typ A max A typ A max A typ A max V min/max Test Conditions/Comments RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 30 RL = 50 , CL = 5 pF; see Figure 31 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 31 f = 1 MHz; VS = 6 V f = 1 MHz; VS = 6 V f = 1 MHz; VS = 6 V VDD = 13.2 V Digital inputs = 0 V or VDD Digital inputs = 5 V Digital inputs = 5 V Ground = 0 V, VSS = 0 V 1.0 58 95 120 190 5/16.5 Guaranteed by design, not subject to production test. 5 V DUAL SUPPLY VDD = +5 V 10%, VSS = -5 V 10%, GND = 0 V, unless otherwise noted. Table 3. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On Resistance Match Between Channels, RON On Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN 25C -40C to +85C -40C to +125C VDD to VSS 4.5 5.2 0.1 0.3 1.3 1.6 0.1 0.5 0.1 0.6 0.1 1 2 3 3 75 100 100 2.0 0.8 0.001 0.1 4 6.2 0.35 1.85 7 0.4 2 Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ Test Conditions/Comments VS = 4.5V, IS = -10 mA; see Figure 22 VDD = +4.5 V, VSS = -4.5 V VS = 4.5V, IS = -10 mA VS = 4.5 V, IS = -10 mA VDD = +5.5 V, VSS = -5.5 V VS = 4.5 V, VD = 4.5 V; see Figure 23 VS = 4.5 V, VD = 4.5 V; see Figure 23 VS = VD = 4.5 V; see Figure 24 VIN = VGND or VDD Rev. 0 | Page 5 of 16 ADG1419 Parameter DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise -3 dB Bandwidth Insertion Loss CS (Off ) CD (Off ) CD, CS (On) POWER REQUIREMENTS IDD ISS VDD/VSS 1 25C 310 410 230 305 220 290 65 59 -60 -60 0.04 105 0.28 26 62 128 0.001 -40C to +85C -40C to +125C Unit ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ MHz typ dB typ pF typ pF typ pF typ A typ A max A typ A max V min/max Test Conditions/Comments RL = 300 , CL = 35 pF VS = 3 V; see Figure 25 RL = 300 , CL = 35 pF VS = 3 V; see Figure 27 RL = 300 , CL = 35 pF VS = 3 V; see Figure 27 RL = 300 , CL = 35 pF VS1 = VS2 = 3 V; see Figure 26 VS = 0 V, RS = 0 , CL = 1 nF; see Figure 28 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 29 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 30 RL = 10 k, 5 V p-p, f = 20 Hz to 20 kHz; see Figure 32 RL = 50 , CL = 5 pF; see Figure 31 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 31 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +5.5 V, VSS = -5.5 V Digital inputs = 0 V or VDD Digital inputs = 0 V or VDD Ground = 0 V 495 355 335 560 390 365 31 1.0 0.001 1.0 4.5/16.5 Guaranteed by design, not subject to production test. CONTINUOUS CURRENT PER CHANNEL, S OR D Table 4. Parameter CONTINUOUS CURRENT PER CHANNEL 1 15 V Dual Supply 8-Lead MSOP (JA = 206C/W) 8-Lead LFCSP (JA = 50.8C/W) +12 V Single Supply 8-Lead MSOP (JA = 206C/W) 8-Lead LFCSP (JA = 50.8C/W) 5 V Dual Supply 8-Lead MSOP (JA = 206C/W) 8-Lead LFCSP (JA = 50.8C/W) 1 25C 85C 125C Unit Test Conditions/Comments VDD = +13.5 V, VSS = -13.5 V 215 390 175 320 165 310 135 215 115 185 110 180 80 100 70 95 70 95 mA maximum mA maximum VDD = 10.8 V, VSS = 0 V mA maximum mA maximum VDD = +4.5 V, VSS = -4.5 V mA maximum mA maximum Guaranteed by design, not subject to production test. Rev. 0 | Page 6 of 16 ADG1419 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Table 5. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs1 Digital Inputs1 Peak Current, S or D (Pulsed at 1 ms, 10% Duty-Cycle Maximum) 8-Lead MSOP (4-Layer Board) 8-Lead LFCSP Continuous Current per Channel, S or D Operating Temperature Range Industrial Storage Temperature Range Junction Temperature Reflow Soldering Peak Temperature, Pb Free 1 THERMAL RESISTANCE Table 6. Thermal Resistance Package Type 8-Lead MSOP (4-Layer Board) 8-Lead LFCSP JA 206 50.8 JC 44 Unit C/W C/W Rating 35 V -0.3 V to +25 V +0.3 V to -25 V VSS - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first GND - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first ESD CAUTION 400 mA 600 mA Data in Table 4 + 15% mA -40C to +125C -65C to +150C 150C 260C Over voltages at IN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 7 of 16 ADG1419 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS D1 SA 2 GND 3 VDD 4 8 SB ADG1419 TOP VIEW (Not to Scale) 7 VSS 6 IN 5 EN 08485-003 D1 SA 2 GND 3 VDD 4 8 SB VSS IN 08485-004 ADG1419 TOP VIEW (Not to Scale) 7 6 5 NOTES 1. EXPOSED PAD TIED TO SUBSTRATE, VSS. NC NC = NO CONNECT Figure 3. 8-Lead LFCSP Pin Configuration Figure 4. 8-Lead MSOP Pin Configuration Table 7. 8-Lead LFCSP Pin Function Descriptions Pin No. 1 2 3 4 5 Mnemonic D SA GND VDD EN Description Drain Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Ground (0 V) Reference. Most Positive Power Supply Potential. Active High Digital Input. When this pin is low, the device is disabled and all switches are turned off. When this pin is high, the IN logic input determines which switch is turned on. Logic Control Input. Most Negative Power Supply Potential. Source Terminal. This pin can be an input or output. Exposed pad tied to substrate, VSS. Table 9. 8-Lead MSOP Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic D SA GND VDD NC IN VSS SB Description Drain Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Ground (0 V) Reference. Most Positive Power Supply Potential. No Connect. Logic Control Input. Most Negative Power Supply Potential. Source Terminal. This pin can be an input or output. 6 7 8 IN VSS SB EPAD Table 10. 8-Lead MSOP Truth Table IN 0 1 Switch A On Off Switch B Off On Table 8. 8-Lead LFCSP Truth Table EN 0 1 1 IN X 0 1 Switch A Off On Off Switch B Off Off On Rev. 0 | Page 8 of 16 ADG1419 TYPICAL PERFORMANCE CHARACTERISTICS 3.5 4.0 TA = 25C VDD = +15V VSS = -15V 3.5 3.0 ON RESISTANCE () ON RESISTANCE () VDD = +10V VSS = -10V 2.5 VDD = +12V VSS = -12V VDD = +13.5V VSS = -13.5V 2.0 3.0 2.5 2.0 1.5 1.0 TA = +125C TA = +85C TA = +25C TA = -40C 1.5 VDD = +15V VSS = -15V 1.0 -16.5 -11.5 -6.5 -1.5 3.5 VS, VD (V) VDD = +16.5V VSS = -16.5V 08485-018 0.5 0 -15 8.5 13.5 -10 -5 0 VS, VD (V) 5 10 15 Figure 5. On Resistance as a Function of VD (VS) for Dual Supply 9 TA = 25C Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures, 15 V Dual Supply 6 8 7 VDD = 15V VSS = 0V 5 TA= +125C ON RESISTANCE () ON RESISTANCE () VDD = 10.8V VSS = 0V 4 TA= +85C 6 5 4 3 2 0 2 4 6 8 VS, VD (V) VDD = 8V VSS = 0V VDD = 12V VSS = 0V VDD = 13.2V VSS = 0V VDD = 15V VSS = 0V 3 TA= +25C TA= -40C 2 1 VDD = 12V VSS = 0V 08485-017 10 12 14 0 2 4 6 VS, VD (V) 8 10 12 Figure 6. On Resistance as a Function of VD (VS) for Single Supply 5.0 Figure 9. On Resistance as a Function of VD (VS) for Different Temperatures, +12 V Single Supply 7 VDD = +5V VSS = -5V TA = 25C 4.5 4.0 VDD = +4.5V VSS = -4.5V 6 ON RESISTANCE () ON RESISTANCE () 3.5 3.0 2.5 2.0 1.5 1.0 0.5 08485-016 5 4 TA = +125C TA = +85C TA = +25C 3 TA = -40C 2 1 VDD = +5V VSS = -5V VDD = +5.5V VSS = -5.5V VDD = +7V VSS = -7V -5 -3 -1 1 3 5 7 -4 -3 -2 -1 0 1 2 3 4 5 VS, VD (V) VS, VD (V) Figure 7. On Resistance as a Function of VD (VS) for Dual Supply Figure 10. On Resistance as a Function of VD (VS) for Different Temperatures, 5 V Dual Supply Rev. 0 | Page 9 of 16 08485-012 0 -7 0 -5 08485-013 0 08485-015 ADG1419 70 60 LEAKAGE CURRENT (nA) VDD = +15V VSS = -15V VBIAS = 10V 90 80 70 60 IDD PER CHANNEL TA = 25C 50 40 30 20 10 0 ID (OFF) - + ID (OFF) + - ID, IS (ON) + + IS (OFF) + - IS (OFF) - + ID, IS (ON) - - IDD (A) 50 40 30 20 10 0 0 2 4 6 8 10 12 14 16 08485-011 08485-010 VDD = +12V VSS = 0V VDD = +15V VSS = -15V VDD = +5V VSS = -5V 0 20 40 60 80 100 120 08485-019 -10 TEMPERATURE (C) -10 LOGIC LEVEL, IN (V) Figure 11. Leakage Currents as a Function of Temperature, 15 V Dual Supply 70 60 VDD = 12V VSS = 0V VBIAS = 1V/10V CHARGE INJECTION (pC) 500 TA = 25C 400 300 Figure 14. IDD vs. Logic Level VDD = +5V VSS = -5V LEAKAGE CURRENT (nA) 50 40 30 20 10 0 -10 0 20 40 60 80 100 120 ID (OFF) - + ID (OFF) + - ID, IS (ON) + + ID, IS (ON) - - IS (OFF) + - IS (OFF) - + 200 100 0 -100 -200 -300 -400 VDD = +15V VSS = -15V VDD = +12V VSS = 0V 08485-032 -5 -10 -15 0 VS (V) 5 10 15 TEMPERATURE (C) Figure 12. Leakage Currents as a Function of Temperature, +12 V Single Supply 60 50 Figure 15. Charge Injection vs. Source Voltage 500 450 400 VDD = +5V VSS = -5V VBIAS = 4.5V LEAKAGE CURRENT (nA) 40 30 20 10 0 ID (OFF) - + ID (OFF) + - IS (OFF) + - IS (OFF) - + ID,IS (ON) + + ID,IS (ON) - - TIME (ns) 350 300 250 200 150 100 50 08485-020 VDD = +5V VSS = -5V VDD = +12V VSS = 0V VDD = +15V VSS = -15V 10 0 20 40 60 80 100 120 TEMPERATURE (C) 0 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) Figure 13. Leakage Currents as a Function of Temperature, 5 V Dual Supply Figure 16. tTRANSITION Times vs. Temperature Rev. 0 | Page 10 of 16 08485-008 -500 ADG1419 0.06 0 TA = 25C VDD = +15V VSS = -15V RL = 110 TA = 25C 0.05 VDD = +5V VSS = -5V VS = 5V p-p -20 OFF ISOLATION (dB) 0.04 THD + N (%) -40 0.03 -60 0.02 -80 0.01 -100 VDD = +15V VSS = -15V VS = 10V p-p 0 08485-006 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) Figure 17. Off Isolation vs. Frequency 0 -10 -20 -30 Figure 20. THD + N vs. Frequency TA = 25C -10 VDD = +15V VSS = -15V -20 -30 0 TA = 25C VDD = +15V VSS = -15V NO DECOUPLING CAPACITORS CROSSTALK (dB) ACPSRR (dB) -40 -50 -60 -70 -80 -90 100k 1M 10M 100M 1G 08485-033 -40 -50 -60 -70 -80 -90 1k 10k 100k FREQUENCY (Hz) 1M 10M 08485-007 DECOUPLING CAPACITORS -100 10k -100 FREQUENCY (Hz) Figure 18. Crosstalk vs. Frequency Figure 21. ACPSRR vs. Frequency 0 -0.5 -1.0 INSERTION LOSS (dB) TA = 25C VDD = +15V VSS = -15V -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 100k 1M 10M 100M 1G 08485-005 -5.0 10k FREQUENCY (Hz) Figure 19. On Response vs. Frequency Rev. 0 | Page 11 of 16 08485-009 -120 1k 0 5k 10k 15k 20k ADG1419 TEST CIRCUITS V ID (ON) S D IDS 08485-021 NC S D A VD 08485-023 VS NC = NO CONNECT Figure 22. On Resistance IS (OFF) A VS S D ID (OFF) A VD 08485-022 Figure 24. On Leakage Figure 23. Off Leakage 0.1F VDD VSS 0.1F VIN 50% 50% VDD VS SB SA IN VIN GND VSS D RL 300 CL 35pF VOUT VIN 50% 90% 50% 90% VOUT tON tOFF Figure 25. Switching Times, tON and tOFF 0.1F VDD VSS 0.1F VIN VDD VS SB SA IN VIN GND VSS D RL 300 CL 35pF VOUT VOUT 80% tBBM tBBM 08485-025 Figure 26. Break-Before-Make Time Delay VDD 3V ENABLE DRIVE (VIN) 0V 50% 50% INx SA SB VS VSS VDD VSS ADG1419 tON (EN) 0.9VO OUTPUT tOFF (EN) 0.9VO VIN 50 EN GND D OUTPUT 300 35pF 08485-026 Figure 27. Enable Delay, tON (EN), tOFF (EN) Rev. 0 | Page 12 of 16 08485-024 ADG1419 0.1F VDD VSS 0.1F VIN (NORMALLY CLOSED SWITCH) ON NC VOUT CL 1nF GND VIN (NORMALLY OPEN SWITCH) VOUT VOUT OFF VDD D VSS SB VS SA IN VIN Figure 28. Charge Injection VDD 0.1F VSS 0.1F NETWORK ANALYZER NC 50 IN VDD 0.1F VSS 0.1F NETWORK ANALYZER NC SA D VDD VSS VDD VSS IN SA D SB 50 VS VOUT SB VS VOUT VIN GND RL 50 VIN GND 08485-028 OFF ISOLATION = 20 log VS INSERTION LOSS = 20 log VOUT WITH SWITCH VOUT WITHOUT SWITCH Figure 29. Off Isolation Figure 31. Bandwidth VDD 0.1F VSS 0.1F VDD 0.1F VSS 0.1F AUDIO PRECISION VDD NETWORK ANALYZER VOUT RL 50 VDD SA VSS SB IN VS GND VSS RS S D R 50 IN D VIN RL 10k GND VOUT VS V p-p CHANNEL-TO-CHANNEL CROSSTALK = 20 log 08485-030 Figure 30. Channel-to-Channel Crosstalk Figure 32. THD + N Rev. 0 | Page 13 of 16 08485-031 VOUT VS 08485-029 VOUT 08485-027 QINJ = CL x VOUT ADG1419 TERMINOLOGY IDD The positive supply current. ISS The negative supply current. VD (VS) The analog voltage on Terminal D and Terminal S. RON The ohmic resistance between Terminal D and Terminal S. RFLAT (ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. IS (Off) The source leakage current with the switch off. ID (Off) The drain leakage current with the switch off. ID, IS (On) The channel leakage current with the switch on. VINL The maximum input voltage for Logic 0. VINH The minimum input voltage for Logic 1. IINL (IINH) The input current of the digital input. CS (Off) The off switch source capacitance, measured with reference to ground. CD (Off) The off switch drain capacitance, measured with reference to ground. CD, CS (On) The on switch capacitance, measured with reference to ground. CIN The digital input capacitance. tON (EN) Delay time between the 50% and 90% points of the digital input and switch on condition. See Figure 27. tOFF (EN) Delay time between the 50% and 90% points of the digital input and switch off condition. See Figure 27. tTRANSITION Delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. TBBM Off time measured between the 80% point of both switches when switching from one address state to another. See Figure 26. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. See Figure 28. Off Isolation A measure of unwanted signal coupling through an off switch. See Figure 29. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. See Figure 30. Bandwidth The frequency at which the output is attenuated by 3 dB. See Figure 31. On Response The frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. See Figure 31. THD + N The ratio of the harmonic amplitude plus noise of the signal to the fundamental. See Figure 32. AC Power Supply Rejection Ratio (ACPSRR) ACPSRR measures the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on the output to the amplitude of the modulation is the ACPSRR. See Figure 21. Rev. 0 | Page 14 of 16 ADG1419 OUTLINE DIMENSIONS 3.20 3.00 2.80 8 5 3.20 3.00 2.80 PIN 1 IDENTIFIER 1 5.15 4.90 4.65 4 0.65 BSC 0.95 0.85 0.75 0.15 0.05 COPLANARITY 0.10 0.40 0.25 15 MAX 1.10 MAX 0.80 0.55 0.40 100709-B 6 0 0.23 0.09 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 33. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 2.00 BSC 1.75 1.65 1.50 5 8 3.00 BSC EXPOSED PAD 1.90 1.80 1.65 1 0.20 MIN 4 INDEX AREA TOP VIEW 0.80 0.75 0.70 SEATING PLANE 0.50 0.40 0.30 0.15 REF PIN 1 INDICATOR BOTTOM VIEW SIDE VIEW Figure 34. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm x 2 mm Body, Very Very Thin, Dual Lead (CP-8-4) Dimensions shown in millimeters ORDERING GUIDE Model ADG1419BRMZ1 ADG1419BRMZ-REEL71 ADG1419BCPZ-REEL71 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C Package Description 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] Package Option RM-8 RM-8 CP-8-4 081806-A 0.50 0.30 0.25 0.20 COPLANARITY 0.08 0.05 MAX 0.02 NOM FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Branding S1L S1L 1C Z = RoHS Compliant Part. Rev. 0 | Page 15 of 16 ADG1419 NOTES (c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08485-0-10/09(0) Rev. 0 | Page 16 of 16 |
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